| United States Patent | 6,849,946 |
| Sethuraman , et al. | February 1, 2005 |
Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
Abstract
The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform. In this manner, dummy conductors spaced apart by dielectric protrusions are formed exclusively in the dummy trenches, and interconnect are formed exclusively in the narrow and wide trenches. The topological surface of the resulting interconnect level is substantially void of surface disparity.
| Inventors: | Sethuraman; Anantha R. (Fremont, CA), Seams; Christopher A. (Pleasanton, CA) |
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| Assignee: | Cypress Semiconductor Corp. (San Jose, CA) |
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| Family ID: | 22505307 |
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| Appl. No.: | 09/779,123 |
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| Filed: | February 7, 2001 |
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