Field
The present disclosure relates generally to electronics, and more specifically to techniques for generating a power supply voltage for a circuit such as an amplifier.
Background
A wireless device (e.g., a cellular phone or a smartphone) in a wireless communication system may transmit and receive data for two-way communication. The wireless device may include a transmitter for data transmission and a receiver for data reception. For data transmission, the transmitter may process (e.g., encode and modulate) data to generate output samples. The transmitter may further condition (e.g., convert to analog, filter, amplify, and frequency upconvert) the output samples to generate a modulated radio frequency (RF) signal, amplify the modulated RF signal to obtain an output RF signal having the proper transmit power level, and transmit the output RF signal via an antenna to a base station. For data reception, the receiver may obtain a received RF signal via the antenna and may amplify and process the received RF signal to recover data sent by the base station.
The transmitter typically includes a power amplifier (PA) to provide high transmit power for the output RF signal. The power amplifier should be able to provide high transmit power and have high power-added efficiency (PAE).
Monday, June 26, 2017
Qualcomm United States Patent 9,535,490 Power saving techniques in computing devices
Field of the Disclosure
The technology of the disclosure relates generally to power saving techniques in computing devices.
Background
Computing devices are common within modem society. Ranging from small, mobile computing devices, such as a smart phone or tablet, to large server farms with numerous blades and memory banks, these devices are expected to communicate across myriad networks while providing various other base functions. While desktop devices and servers are generally immune to concerns about power consumption, mobile devices constantly struggle to find a proper balance between available functions and battery life. That is, as more functions are provided, power consumption increases, and battery life is shortened. Servers may likewise have power consumption concerns when assembled in large server farms.
Concurrent with power consumption concerns, improvements in network communications have increased data rates. For example, copper wires have been replaced with higher bandwidth fiber optic cables, and cellular networks have evolved from early Advanced Mobile Phone System (AMPS) and Global System for Mobile Communications (GSM) protocols to 4G and Long Term Evolution (LTE) protocols capable of supporting much higher data rates. As the data rates have increased, the need to be able to process these increased data rates within computing devices has also increased. Thus, earlier mobile computing devices may have had internal buses formed according to a High Speed Inter-Chip (HSIC) standard, universal serial bus (USB) standard (and particularly USB 2.0), or universal asynchronous receiver/transmitter (UART) standard. However, these buses do not support current data rates.
In response to the need for faster internal buses, the peripheral component interconnect express (PCIe) standard, as well as, later generations of USB (e.g., USB 3.0 and subsequent versions) have been adopted for some mobile computing devices. However, while PCIe and USB 3.0 can handle the high data rates currently being used, usage of such buses results in excessive power consumption and negatively impacts battery life by shortening the time between recharging events.
The technology of the disclosure relates generally to power saving techniques in computing devices.
Background
Computing devices are common within modem society. Ranging from small, mobile computing devices, such as a smart phone or tablet, to large server farms with numerous blades and memory banks, these devices are expected to communicate across myriad networks while providing various other base functions. While desktop devices and servers are generally immune to concerns about power consumption, mobile devices constantly struggle to find a proper balance between available functions and battery life. That is, as more functions are provided, power consumption increases, and battery life is shortened. Servers may likewise have power consumption concerns when assembled in large server farms.
Concurrent with power consumption concerns, improvements in network communications have increased data rates. For example, copper wires have been replaced with higher bandwidth fiber optic cables, and cellular networks have evolved from early Advanced Mobile Phone System (AMPS) and Global System for Mobile Communications (GSM) protocols to 4G and Long Term Evolution (LTE) protocols capable of supporting much higher data rates. As the data rates have increased, the need to be able to process these increased data rates within computing devices has also increased. Thus, earlier mobile computing devices may have had internal buses formed according to a High Speed Inter-Chip (HSIC) standard, universal serial bus (USB) standard (and particularly USB 2.0), or universal asynchronous receiver/transmitter (UART) standard. However, these buses do not support current data rates.
In response to the need for faster internal buses, the peripheral component interconnect express (PCIe) standard, as well as, later generations of USB (e.g., USB 3.0 and subsequent versions) have been adopted for some mobile computing devices. However, while PCIe and USB 3.0 can handle the high data rates currently being used, usage of such buses results in excessive power consumption and negatively impacts battery life by shortening the time between recharging events.
Qualcomm US Patent 8,838,949 Direct scatter loading of executable software image from a primary processor to one or more secondary processor in a multi-processor system
BACKGROUND
Processors execute software code to perform operations. Processors may require some software code, commonly referred to as boot code, to be executed for hooting up. In a multi-processor system, each processor may require respective boot code for booting up. As an example, in a smartphone device that includes an application processor and a modem processor, each of the processors may have respective boot code for booting up.
A problem exists on a significant number of devices (such as smart phones) that incorporate multiple processors (e.g., a standalone application processor chip integrated with a separate modem processor chip). A flash/non-volatile memory component may be used for each of the processors, because each processor has non-volatile memory (e.g., persistent storage) of executable images and file systems. For instance, a processor's boot code may be stored to the processor's respective non-volatile memory (e.g., Flash memory, read-only memory (ROM), etc.), and upon power-up the boot code software is loaded for execution by the processor from its respective non-volatile memory. Thus, in this type of architecture the executable software, such as a processor's boot code, is not required to be loaded to the processor from another processor in the system.
Adding dedicated non-volatile memory to each processor, however, occupies more circuit board space, thereby increasing the circuit board size. Some designs may use a combined chip for Random Access Memory (RAM) and Flash memory (where RAM and Flash devices are stacked as one package to reduce size) to reduce board size. While multi-chip package solutions do reduce the needed circuit board foot print to some extent, it may increase costs.
In some multi-processor systems, software may be required to be loaded to one processor from another processor. For example, suppose a first processor in a multi-processor system is responsible for storing to its non-volatile memory boot code for one or more other processors in the system; wherein upon power-up the first processor is tasked with loading the respective boot code to the other processor(s), as opposed to such boot code residing in non-volatile memory of the other processor(s). In this type of system, the software (e.g., boot image) is downloaded from the first processor to the other processor(s) (e.g., to volatile memory of the other processor(s)), and thereafter the receiving processor(s) boots with the downloaded image.
Often, the software image to be loaded is a binary multi-segmented image. For instance, the software image may include a header followed by multiple segments of code. When software images are loaded, from an external device (e.g., from another processor) onto a target device (e.g., a target processor) there may be an intermediate step where the binary multi-segmented image is transferred into the system memory and then later transferred into target locations by the boot loader.
In a system in Which the software image is loaded onto a target "secondary" processor from a first "primary" processor, one way of performing such loading is to allocate a temporary buffer into which each packet is received, and each packet would have an associated packet header information along with the payload. The payload in this case would be the actual image data. From the temporary buffer, some of the processing may be done over the payload, and then the payload would get copied over to the final destination. The temporary buffer would be some place in system memory, such as in internal random-access-memory (RAM) or double data rate (DDR) memory, for example.
Thus, where an intermediate buffer is used, the data being downloaded from a primary processor to a secondary processor is copied into the intermediate buffer. In this way, the buffer is used to receive part of the image data from the primary processor, and from the buffer the image data may be scattered into the memory (e.g., volatile memory) of the secondary processor.
The primary processor and its non-volatile memory that stores the boot image for a secondary processor may be implemented on a different chip than a chip on which the secondary processor is implemented. Thus, in order to transfer the data from the primary processor's non-volatile memory to the secondary processor (e.g., to the secondary processor's volatile memory), a packet-based communication may be employed, wherein a packet header is included in each packet communicated to the secondary processor. The packets are stored in an intermediate buffer, and some processing of the received packets is then required for that data to be stored where it needs to go (e.g., within the secondary processor's volatile memory).
Processors execute software code to perform operations. Processors may require some software code, commonly referred to as boot code, to be executed for hooting up. In a multi-processor system, each processor may require respective boot code for booting up. As an example, in a smartphone device that includes an application processor and a modem processor, each of the processors may have respective boot code for booting up.
A problem exists on a significant number of devices (such as smart phones) that incorporate multiple processors (e.g., a standalone application processor chip integrated with a separate modem processor chip). A flash/non-volatile memory component may be used for each of the processors, because each processor has non-volatile memory (e.g., persistent storage) of executable images and file systems. For instance, a processor's boot code may be stored to the processor's respective non-volatile memory (e.g., Flash memory, read-only memory (ROM), etc.), and upon power-up the boot code software is loaded for execution by the processor from its respective non-volatile memory. Thus, in this type of architecture the executable software, such as a processor's boot code, is not required to be loaded to the processor from another processor in the system.
Adding dedicated non-volatile memory to each processor, however, occupies more circuit board space, thereby increasing the circuit board size. Some designs may use a combined chip for Random Access Memory (RAM) and Flash memory (where RAM and Flash devices are stacked as one package to reduce size) to reduce board size. While multi-chip package solutions do reduce the needed circuit board foot print to some extent, it may increase costs.
In some multi-processor systems, software may be required to be loaded to one processor from another processor. For example, suppose a first processor in a multi-processor system is responsible for storing to its non-volatile memory boot code for one or more other processors in the system; wherein upon power-up the first processor is tasked with loading the respective boot code to the other processor(s), as opposed to such boot code residing in non-volatile memory of the other processor(s). In this type of system, the software (e.g., boot image) is downloaded from the first processor to the other processor(s) (e.g., to volatile memory of the other processor(s)), and thereafter the receiving processor(s) boots with the downloaded image.
Often, the software image to be loaded is a binary multi-segmented image. For instance, the software image may include a header followed by multiple segments of code. When software images are loaded, from an external device (e.g., from another processor) onto a target device (e.g., a target processor) there may be an intermediate step where the binary multi-segmented image is transferred into the system memory and then later transferred into target locations by the boot loader.
In a system in Which the software image is loaded onto a target "secondary" processor from a first "primary" processor, one way of performing such loading is to allocate a temporary buffer into which each packet is received, and each packet would have an associated packet header information along with the payload. The payload in this case would be the actual image data. From the temporary buffer, some of the processing may be done over the payload, and then the payload would get copied over to the final destination. The temporary buffer would be some place in system memory, such as in internal random-access-memory (RAM) or double data rate (DDR) memory, for example.
Thus, where an intermediate buffer is used, the data being downloaded from a primary processor to a secondary processor is copied into the intermediate buffer. In this way, the buffer is used to receive part of the image data from the primary processor, and from the buffer the image data may be scattered into the memory (e.g., volatile memory) of the secondary processor.
The primary processor and its non-volatile memory that stores the boot image for a secondary processor may be implemented on a different chip than a chip on which the secondary processor is implemented. Thus, in order to transfer the data from the primary processor's non-volatile memory to the secondary processor (e.g., to the secondary processor's volatile memory), a packet-based communication may be employed, wherein a packet header is included in each packet communicated to the secondary processor. The packets are stored in an intermediate buffer, and some processing of the received packets is then required for that data to be stored where it needs to go (e.g., within the secondary processor's volatile memory).
Qualcomm US Patent 8,487,658 Compact and robust level shifter layout design
BACKGROUND
Integrated circuit devices containing several types of functional circuit are sometimes required to handle a plurality of voltage levels. Such devices are often known as multi-voltage level devices. Multi-voltage level devices contain a high-voltage circuit driven by a relatively high voltage power supply and a low-voltage circuit driven by a relatively low-voltage power supply. Multi-voltage circuits include but are not limited to voltage level shifters (VLS), isolation cell, retention registers, always on logic and similar components.
Power consumption of integrated circuits may be reduced and efficiencies may be increased by reducing operating voltages of the integrated circuits. Some circuits are more amenable to lower operating voltages than others. Where integrated circuits within a system operate at lower voltages, conflicts or contention may arise between the circuits. These conflicts and contention can be alleviated by level shifting the operating voltage of part of the circuits to higher voltage. But level shifting may introduce delays.
Technology scaling reduces the delay of circuit elements, enhancing the operating frequency of an integrated circuit (IC) device. The density and number of transistors on an IC are increased by scaling the feature size. By utilizing this growing number of available transistors in each new technology, novel circuit techniques can be employed further enhancing the performance of the ICs beyond the levels made possible by simply shrinking.
Integrated circuit devices containing several types of functional circuit are sometimes required to handle a plurality of voltage levels. Such devices are often known as multi-voltage level devices. Multi-voltage level devices contain a high-voltage circuit driven by a relatively high voltage power supply and a low-voltage circuit driven by a relatively low-voltage power supply. Multi-voltage circuits include but are not limited to voltage level shifters (VLS), isolation cell, retention registers, always on logic and similar components.
Power consumption of integrated circuits may be reduced and efficiencies may be increased by reducing operating voltages of the integrated circuits. Some circuits are more amenable to lower operating voltages than others. Where integrated circuits within a system operate at lower voltages, conflicts or contention may arise between the circuits. These conflicts and contention can be alleviated by level shifting the operating voltage of part of the circuits to higher voltage. But level shifting may introduce delays.
Technology scaling reduces the delay of circuit elements, enhancing the operating frequency of an integrated circuit (IC) device. The density and number of transistors on an IC are increased by scaling the feature size. By utilizing this growing number of available transistors in each new technology, novel circuit techniques can be employed further enhancing the performance of the ICs beyond the levels made possible by simply shrinking.
Qualcomm United States Patent 8,698,558 Low-voltage power-efficient envelope tracker
Background
In a communication system, a transmitter may process (e.g., encode and modulate) data to generate output samples. The transmitter may further condition (e.g., convert to analog, filter, frequency upconvert, and amplify) the output samples to generate an output radio frequency (RF) signal. The transmitter may then transmit the output RF signal via a communication channel to a receiver. The receiver may receive the transmitted RF signal and perform the complementary processing on the received RF signal to recover the transmitted data.
The transmitter typically includes a power amplifier (PA) to provide high transmit power for the output RF signal. The power amplifier should be able to provide high output power and have high power-added efficiency (PAE). Furthermore, the power amplifier may be required to have good performance and high PAE even with a low battery voltage.
In a communication system, a transmitter may process (e.g., encode and modulate) data to generate output samples. The transmitter may further condition (e.g., convert to analog, filter, frequency upconvert, and amplify) the output samples to generate an output radio frequency (RF) signal. The transmitter may then transmit the output RF signal via a communication channel to a receiver. The receiver may receive the transmitted RF signal and perform the complementary processing on the received RF signal to recover the transmitted data.
The transmitter typically includes a power amplifier (PA) to provide high transmit power for the output RF signal. The power amplifier should be able to provide high output power and have high power-added efficiency (PAE). Furthermore, the power amplifier may be required to have good performance and high PAE even with a low battery voltage.
Qualcomm US Patent 8,633,936 Programmable streaming processor with mixed precision instruction execution
BACKGROUND
Graphics devices are widely used to render 2-dimensional (2-D) and 3-dimensional (3-D) images for various applications, such as video games, graphics programs, computer-aided design (CAD) applications, simulation and visualization tools, imaging, and the like. A graphics device may perform various graphics operations to render an image. The graphics operations may include rasterization, stencil and depth tests, texture mapping, shading, and the like. A 3-D image may be modeled with surfaces, and each surface may be approximated with polygons, such as triangles. The number of triangles used to represent a 3-D image for rendering purposes is dependent on the complexity of the surfaces as well as the desired resolution of the image.
Each triangle may be defined by three vertices, and each vertex is associated with various attributes such as space coordinates, color values, and texture coordinates. When a graphics device uses a vertex processor during the rendering process, the vertex processor may process vertices of the various triangles. Each triangle is also composed of picture elements (pixels). When the graphics device also, or separately, uses a pixel processor during the rendering process, the pixel processor renders each triangle by determining the values of the components of each pixel within the triangle.
In many cases, a graphics device may utilize a shader processor to perform certain graphics operations such as shading. Shading is a highly complex graphics operation involving lighting and shadowing. The shader processor may need to execute a variety of different instructions when performing rendering, and typically includes one or more execution units to aid in the execution of these instructions. For example, the shader processor may include arithmetic logic units (ALU's) and/or an elementary functional unit (EFU) as execution units. Often, these execution units are capable of executing instructions using full data-precision circuitry. However, such circuitry can often require more power, and the execution units may take up more physical space within the shader processor integrated circuit used by the graphics device.
Graphics devices are widely used to render 2-dimensional (2-D) and 3-dimensional (3-D) images for various applications, such as video games, graphics programs, computer-aided design (CAD) applications, simulation and visualization tools, imaging, and the like. A graphics device may perform various graphics operations to render an image. The graphics operations may include rasterization, stencil and depth tests, texture mapping, shading, and the like. A 3-D image may be modeled with surfaces, and each surface may be approximated with polygons, such as triangles. The number of triangles used to represent a 3-D image for rendering purposes is dependent on the complexity of the surfaces as well as the desired resolution of the image.
Each triangle may be defined by three vertices, and each vertex is associated with various attributes such as space coordinates, color values, and texture coordinates. When a graphics device uses a vertex processor during the rendering process, the vertex processor may process vertices of the various triangles. Each triangle is also composed of picture elements (pixels). When the graphics device also, or separately, uses a pixel processor during the rendering process, the pixel processor renders each triangle by determining the values of the components of each pixel within the triangle.
In many cases, a graphics device may utilize a shader processor to perform certain graphics operations such as shading. Shading is a highly complex graphics operation involving lighting and shadowing. The shader processor may need to execute a variety of different instructions when performing rendering, and typically includes one or more execution units to aid in the execution of these instructions. For example, the shader processor may include arithmetic logic units (ALU's) and/or an elementary functional unit (EFU) as execution units. Often, these execution units are capable of executing instructions using full data-precision circuitry. However, such circuitry can often require more power, and the execution units may take up more physical space within the shader processor integrated circuit used by the graphics device.
Sunday, June 25, 2017
Samsung's foldable television display panel - United States Patent D789,900
| United States Patent | D789,900 |
| Lee , et al. | June 20, 2017 |
Television
CLAIM We claim the ornamental design for a television, as shown and described.
| Inventors: | Lee; Hyungsun (Yongin-si, KR), Kim; Daejoong (Seoul, KR), Lim; Jisoo (Seoul, KR), Kim; Jeasung (Hwaseong-si, KR), Lee; Sangyoung (Anyang-si,KR), Lee; Joonyoung (Seoul, KR), Jeong; Heeseok (Suwon-si, KR), Cho; Kyuhyun (Suwon-si, KR), Cho; Shiyun (Anyang-si, KR), Choi; Younho (Seoul,KR) | ||||||||||
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| Applicant: |
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| Assignee: | Samsung Electronics Co., Ltd. (Suwon-si, KR) | ||||||||||
| Appl. No.: | D/565,978 | ||||||||||
| Filed: | May 26, 2016 |
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